About me
I am a full-time Verification Engineer at SiSoC Semiconductor Technologies, working on Design and Verification of a RISC-V CPU/SoC.
Research Interests
- Advanced Computer Architecture and Organization
- Processor Architecture/Micro-architecture Design Verification
- Energy Efficient Computing(High Performance Computing/Power-wall bottleneck/Memory scaling/Interconnects)
- AI for HPC & HPC for AI
- Generative AI for Hardware Design and Verification
- AI hardware accelerators
- Human-Computer Interaction(HCI)/Neuromorphic chips
- Y86-64/RISC-V CPU/SoC Design and Verification(Digital VLSI)
- CPU/GPU/TPU/NPU/APU/XPU/HPC
Career Overview
- [Feb, 2024 - Present] Full-time Verification Engineer at SiSoC Semiconductor Technologies.[Heterogeneous architectures] - Hiring and mentoring employees(High-End RISC-V CPU Design & Verification from scratch) - X86/ARM/RISC-V(exploring advanced computer architecture and broad spectrum of VLSI, LLVM, and Compilers, Utilizing open-source emulators(GEM5) & simulator(ChampSim), cloud-based computing(Git codespace, jupyter notebook for various architectural & micro-architectural analysis, performance modeling.
- [February, 2023 - Nov, 2023] Verification Engineer at Chiplogic Technologies[RISC-V Architecture Verification, Codasip client].
- [September, 2021 - Dec, 2022] Verification Engineer at Scaledge Technology[RISC-V Verification(CVA6 and Ibex core), ASIC Verification Engineer, Intel client].
- Worked on DFD project.
- Internships
- [March, 2021 - Sep, 2021] Functional Verification(DV Trainee).
- Digital Design, Verilog, SystemVerilog, UVM.
- [Jan, 2020 - Nov, 2020] Worked at Sakthi CADD as Embedded Hardware Design Engineer.
- [2015 - 2019] B.E from IES College Of Technnology, Bhopal.