MOOC Courses
Saylor Academy, CS301: Computer Architecture
- Pipelining
- Caches, coherency protocols
- Superscalar and VLIW
Armv8 Architecture: Exception Level and Exception State
- Arm Architecture
- Arm Cortex
SoC Verification using SystemVerilog
Hello FPGA
TCP on FPGA made practical and fast
Computer Vision: Object Tracking with OpenCV & Python
Developing FPGA-accelerated cloud applications with SDAccel: Theory
FPGA Computing Systems: Background knowledge and introductory materials
- Basics and advanced concepts of FPGA
Hands-On AI/ML Cloud Study Jam, GDG cloud, Palo Alto
- Training dataset and inferencing
- Neural Network architecture and applications(CNN, ANN, BNN SNN)
- K-Means clustering
- Pruning
- Python
- Jupyter Notebook and Google Colaboratory
- Image recognition
Industrial Training on Embedded Systems and PCB Designing
- 8085, 8086
- Arduino, Raspberry Pi
- 2 layer PCB
Embedded systems and VLSI Design
- Keil and Proteus tool
- Embedded C
- Verilog code for Traffic signals
8051 Embedded Systems Workshop
- Keil-Arm MCU
- 8051 concepts and programming
Workshop in PCB Designing and Robotics
- PCB design steps and creation
- Drone design
35th international conference on VLSI Design
- Conference on VLSI Design
- past, present and Future in VLSI Space
CPU Design using Verilog
- Single-cycle, multi-cycle and Pipelined processor
- Multithreaded and Multi-core processor
- Pipelined CPU with FPU
Machine Learning on Hardware
- Verilog
- Neural Networks for Gates, Muxes and RAM
- Google colab
- Quartus Prime and ModelSim
Online Training program on VLSI SYSTEM DESIGN USING OPEN-SOURCE EDA
- Intro to Raven chip, risc-architecture
- EDA Tools
- Ngspice –> General purpose circuit simulation program for non-linear and linear analyses.
- Magic –> VLSI Layout editor, extraction and DRC tool.
- Opentimer –> Open-source high performance timing analysis tool.
- eSim –> Complex Circuit design, SPICE simulation, analysis and PCB design.
- Qflow –> Tool chain (like Yosys, Graywolf) for complete RTL2GDS flow.
SoC Design using OpenPOWER Cores
- IBM OpenPower processsor
- From RTL to GDSII using OpenLane(Microwatt, Litex SoC, MicroPython)
- Simulation with FPGA
- Design and development of a SoC
SystemVerilog for verification part 2: projects
- D-FF, FIFO
- I2C, SPI, & UART
- APB, AHB, & AXI
- Wishbone
UVM for verification part 2: projects
- D-FF
- UART, I2C, SPI
- APB, AXI and demonstration of virtual sequencer and sequence library
- TLM Analysis FIFO
2nd workshop on RISC-V and OpenPOWER in HPC at the ICS International Conference on Supercomputing 2021
