DIY Projects
My Self Explored MS/PhD courses & Projects(Computer Architecture and Organization, VLSI Design, Verification) in progress
Self taught MS EECS Courses(UC Berkeley, MIT, USC, CMU, GeorgiaTech, & Stanford)
- CS 61C: Great Ideas of Computer Architecture(Machine Structures)(UC Berkeley)
- CS 152: Computer Architecture & Engineering(UC Berkeley)
- CS 252: Graduate Computer Architecture(UC Berkeley)
- CS 203: Advanced Computer Architecture(x86)(UC Riverside)
- 18-447: RISC-V Edition(1. Microprocessors, 2. Memory & I/O, 3. Parallel Computer Architecture)(CMU)
- CS 250: VLSI System Design(UC Berkeley)
- EE599: Verification of VLSI Systems(USC)
- 18-600: Foundations of computer Systems, (CS:APP3e book) (CMU)
- ECE 8893B: Hardware Acceleration for Machine Learning(Georgia Institute Of Technology)
- CS 217: Hardware Accelerators for Machine Learning(Stanford)
Related Projects(in progress)
32-bit Out-Of-Order Tomasulo Execution Engine
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Functional Verification of MESI protocol based L1 cache coherent system
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Simulator for LC-3b ISA
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Branch Predictors(global 2-bit, bimodal, and correlated) and Branch predictor simulator
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Cache & Memory Hierarchy Design simulator
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Design CAM unit and LRU stack using verilog and simulate on Modelsim
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Y86-64 CPU design and formal verification
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Chip Multiprocessor with core multithreading
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Out-Of-Order MIPS R10K style processor design based on RISC-V ISA and an In-Order CPU based on RISC-V ISA
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FPGA Design of superscalar out-of-order processor
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Reed Solomon Error correction code decoder hardware accelerator
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Improving Cache efficiency by exploiting read-write disparity
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Processor Beyond
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Formal Verification of cache coherence protocol using Murphi
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Binary Artificial Neural network using Verilog - ASIC & FPGA Design with verilog
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Superscalar Pipeline Simulator
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cva6, OpenPiton, Mor1kx, and CLARVI ---- ONGOING MY PERSONAL RESEARCH
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SMT based GPGPU Design
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AXI Interconnect Network and Simulate
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DLX processor design
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